CVE-2026-23554 — Use after free of paging structures in EPT
The Intel EPT paging code uses an optimization to defer flushing of any cached EPT state until the p2m lock is dropped, so that multiple modifications done under the same locked…
Published: 2026-03-23 · CVSS: 7.8 · CVSS 3.1
The Intel EPT paging code uses an optimization to defer flushing of any cached EPT state until the p2m lock is dropped, so that multiple modifications done under the same locked region only issue a single flush. Freeing of paging structures however is not deferred until the flushing is done, and can result in freed pages transiently being present in cached state. Such stale entries can point to memory ranges not owned by the guest, thus allowing access to unintended memory regions.
Source: CVE Program · Revision 8b16575c39f1e1810c5e863010da073d2d3285e7